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TM
HSP45116/883
Data Sheet May 1999 FN2813.3
Numerically Controlled Oscillator/Modulator
The Intersil HSP45116/883 combines a high performance quadrature numerically controlled oscillator (NCO) and a high speed 16-bit Complex Multiplier/Accumulator (CMAC) on a single IC. This combination of functions allows a complex vector to be multiplied by the internally generated (cos, sin) vector for quadrature modulation and demodulation. As shown in the Block Diagram, the HSP45116/883 is divided into three main sections. The Phase/Frequency Control Section (PFCS) and the Sine/Cosine Section together form a complex NCO. The CMAC multiplies the output of the Sine/Cosine Section with an external complex vector. The inputs to the Phase/Frequency Control Section consist of a microprocessor interface and individual control lines. The phase resolution of the PFCS is 32 bits, which results in frequency resolution better than 0.006Hz at 25.6MHz. The output of the PFCS is the argument of the sine and cosine. The spurious free dynamic range of the complex sinusoid is greater than 90dBc. The output vector from the Sine/Cosine Section is one of the inputs to the Complex Multiplier/Accumulator. The CMAC multiplies this (cos, sin) vector by an external complex vector and can accumulate the result. The resulting complex vectors are available through two 20-bit output ports which maintain the 90dB spectral purity. This result can be accumulated internally to implement an accumulate and dump filter. A quadrature down converter can be implemented by loading a center frequency into the Phase/Frequency Control Section. The signal to be downconverted is the Vector Input of the CMAC, which multiplies the data by the rotating vector from the Sine/Cosine Section. The resulting complex output is the down converted signal.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * NCO and CMAC on One Chip * 15MHz and 25.6MHz Versions * 32-Bit Frequency Control * 16-Bit Phase Modulation * 16-Bit CMAC * 0.006Hz Tuning Resolution at 25.6MHz * Spurious Frequency Components < -90dBc * Fully Static CMOS
Applications
* Frequency Synthesis * Modulation - AM, FM, PSK, FSK, QAM * Demodulation, PLL * Phase Shifter * Polar to Cartesian Conversions
Ordering Information
PART NUMBER HSP45116GM-15/883 HS45116GM-25/883 TEMP. RANGE ( oC) -55 to 125 -55 to 125 PACKAGE 145 Ld PGA 145 Ld PGA PKG. NO. G145.A G145.A
Block Diagram
VECTOR INPUT R SINE/ COSINE ARGUMENT I
MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS
PHASE/ FREQUENCY CONTROL SECTION
SIN SINE/ COSINE SECTION COS CMAC
R
I
VECTOR OUTPUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HSP45116/883
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input or Output Voltage Applied. . . . . . . . . GND -0.5V to VCC +0.5V ESD Rating Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC ( oC/W) PGA Package . . . . . . . . . . . . . . . . . . . 30.0 5.0 Maximum Package Power Dissipation at 125oC PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.16W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Number of Transistors or Gates . . . . . . . . . . . . 103,000 Transistors
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER Logical One Input Voltage Logical Zero Input Voltage Logical One Input Voltage Clock Logical Zero Input Voltage Clock Output HIGH Voltage SYMBOL VIH VIL TEST CONDITIONS VCC = 5.5V VCC = 4.5V GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE (oC) 55 TA 125 55 TA 125 55 TA 125 55 TA 125 55 TA 125 55 TA 125 55 TA 125 55 TA 125 55 TA 125 55 TA 125 MIN 2.2 MAX UNITS V
1, 2, 3
-
0.8
V
VIHC
VCC = 5.5V
1, 2, 3
3.0
-
V
VILC
VCC = 4.5V
1, 2, 3
-
0.8
V
VOH V OL II IO
IOH = -400A VCC = 4.5V (Note 2) IOL = +2.0mA VCC = 4.5V (Note 2) VIN = VCC or GND VCC = 5.5V VOUT = VCC or GND VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, (Note 5) f = 15MHz, VIN = VCC or GND VCC = 5.5V (Notes 3, 5) (Note 4)
1, 2, 3
2.6
-
V
Output LOW Voltage
1, 2, 3
-
0.4
V A A A
Input Leakage Current
1, 2, 3
-10
+10
Output or I/O Leakage Current Standby Power Supply Current Operating Power Supply Current
1, 2, 3
-10
+10
ICCSB
1, 2, 3
-
500
ICCOP
1, 2, 3
-
150
mA
Functional Test NOTES:
FT
7, 8
55 TA 125
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating Supply Current is proportional to frequency, typical rating is 10mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.4V, VIH (all other inputs) = 2.6V, VIL = 0.4V, VOH 1.5V, and VOL 1.5V. 5. Output per test load circuit with switch open and CL = 40pF.
2
HSP45116/883
TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested -15 (15MHz) PARAMETER CLK Period CLK High CLK Low WR Low WR High Setup Time; ADO-1, CS to WR Going High Hold Time; AD0, AD1, CS from WR Going High Setup Time CO-15 from WR Going High Hold Time CO-15 from WR Going High Setup Time WR to CLK High Setup Time MODO-1 to CLK Going High Hold Time MODO-1 from CLK Going High Setup Time PACI to CLK Going High Hold Time PACI from CLK Going High Setup Time ENPHREG, ENCFRCTL, ENPHAC, ENTICTL, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SHO-1, RBYTILD from CLK Going High Hold Time ENPHREG, ENCFRCTL, ENPHAC, ENTICTL, CLROFR, PMSEL, LOAD, ENI, ACC, BINFMT, PEAK, MODPI/2PI, SHO-1, RBYTILD from CLK Going High Setup Time RINO-18, IMINO-18 to CLK Going High Hold Time RINO-18, IMINO-18, to CLK Going High CLK to Output Delay R0O-19, I0O-19 SYMBOL tCP tCH tCL tWL tWH tAWS NOTES GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 66 26 26 26 26 20 MAX -25 (25.6MHz) MIN 39 15 -15 15 15 18 MAX UNITS ns ns ns ns ns ns
tAWH
9, 10, 11
0
-
0
-
ns
tCWS
9, 10, 11
20
-
18
-
ns
tCWA
9, 10, 11
0
-
0
-
ns
tWC tMCS
(Note 7)
9, 10, 11 9, 10, 11
20 20
-
16 18
-
ns ns
tMCH
9, 10, 11
0
-
0
-
ns
tPCS
9, 10, 11
25
-
18
-
ns
tPCH
9, 10, 11
0
-
0
-
ns
tECS
9, 10, 11
20
-
15
-
ns
tECH
9, 10, 11
-55 TA 125
0
-
0
-
ns
tDS
9, 10, 11
-55 TA 125 -55 TA 125 -55 TA 125
20
-
15
-
ns
tDH
9, 10, 11
0
-
0
-
ns
tDO
9, 10, 11
40
-
25
-
ns
3
HSP45116/883
TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested -15 (15MHz) PARAMETER CLK to Output Delay DETO-1 CLK to Output Delay PACO CLK to Output Delay TICO Output Enable Time OER, OEI, OEREXT, OEIEXT OUTMUXO-1 to Output Delay NOTES: 6. AC testing is performed as follows: VCC = 4.5V and 5.5V. Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 3.0V and 0V; timing reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with switch closed and CL = 40pF. Output transition is measured at VOH 1.5V and V OL 1.5V. 7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active. 8. Transition is measured at 200mV from steady state voltage, output loading per test load circuit, with switch closed and CL = 40pF. TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS TEMPERATURE (oC) TA - +25 -15 MIN MAX 15 MIN -25 MAX 15 UNITS pF SYMBOL tDEO tPO tTO tOE (Note 8) NOTES GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 40 MAX 30 30 25 -25 (25.6MHz) MIN 27 MAX 20 20 20 UNITS ns ns ns ns
tMD
9, 10, 11
-
40
-
28
ns
PARAMETER Input Capacitance
SYMBOL CIN
TEST CONDITIONS VCC = Open, f = 1MHz All measurements are referenced to device GND
NOTES 9
Output Capacitance Output Disable Time Output Rise Time Output Fall Time NOTES:
COUT tOD tR tF From 0.8V to 2.0V From 2.0V to 0.8V
9 9, 10 9, 10 9, 10
TA - +25 -55 TA 125 -55 TA 125 -55 TA 125
-
15 20 8 8
-
15 15 8 8
pF ns ns ns
9. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Tess Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100% 100% Samples SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
4
HSP45116/883 Burn-In Circuit
145 PIN PGA TOP VIEW
1 A VCC
2 IMIN4
3 IMIN8
4 IMIN9
5
6
7
8 GND
9 VCC
10 IO18
11 IO15
12 IO12
13 IO10
14 GND
15 VCC A
IMIN11 IMIN15 IMIN16
B
GND
IMIN 1
IMIN5
IMIN7
IMIN10 IMIN13 IMIN14
IO19
IO16
IO14
IO11
IO8
IO7
IO5
IO2
B
C
RIN15
RIN18
IMIN2
IMIN3
IMIN6
IMIN12 IMIN17 IMIN18
IO17
IO13
IO9
IO6
IO4
IO1
RO18
C
D
RIN13
RIN17
IMIN0
INDEX
IO3
RO19
RO17
D
E
RIN10
RIN14
RIN16
IO0
RO16
RO15
E
F
RIN7
RIN11
RIN12
RO14
RO13
RO11
F
G
VCC
RIN9
RIN8
RO9
RO12
RO10
G
H
GND
RIN6
RIN5
RO8
RO7
GND
H
J
RIN3
RIN1
RIN4
RO5
RO4
VCC
J
K
RIN2
RIN0
SH1
RO1
RO2
RO6
K
L
SH0 ENPH REG
ACC
RBYTILD
PACO
DET1
RO3
L
M
PEAK
MOD1 ENCF REG MODPI /2PI CS OUTMUX1
OEREXT
OEI
RO0
M
N
ENOF REG BINFMT MOD0
LOAD
AD0
C14
C13
C8
C2
OUTMUX0
OEIEXT
DET0
N
P
TICO
PACI
PMSEL CLROFR ENTIREG
AD1
C15
C10
C9
C6
C3
C1
OER
GND
P
Q
VCC 1
GND 2
ENPHAC
ENI 4
CLK 5
WR 6
VCC 7
GND 8
C12 9
C11 10
C7 11
C5 12
C4 13
C0 14
VCC 15
Q
3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 5
HSP45116/883 Burn-in Circuit
PGA PIN D3 C2 D2 E3 C1 E2 D1 F3 F2 E1 G2 G3 F1 H2 H3 J3 J1 K1 J2 K2 K3 L1 L2 M1 N1 M2 L3 N2 P1 M3 N3 P2 N4 P3 P4 N5 NOTE: 11. 47k 20%) resistor connected to all pins except VCC and GND. 12. V CC = 5.5V 0.5V with 0.1F (min) capacitor between VCC and GND per position. 13. F0 = 100kHz 10%, F1 = F0/2, F2 = F1/2 . . . . . , F11 = F10/2, 40% to 60% duty cycle. 14. Input Voltage limits: V IL = 0.8V max, VIH = 4.5V 10%. PIN NAME IMIN(0) RIN(18) RIN(17) RIN(16) RIN(15) RIN(14) RIN(13) RIN(12) RIN(11) RIN(10) RIN(9) RIN(8) RIN(7) RIN(6) RIN(5) RIN(4) RIN(3) RIN(2) RIN(1) RIN(0) SH(1) SH(0) ACC ENPHREG ENOFREG PEAK RBYTILD BINFMT TICO MOD(1) MOD(0) PACI LOAD PMSEL CLROFR ENCFREG BURN-INSIGNAL F4 F9 F8 F7 F6 F5 F4 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F4 F16 F4 F8 F16 F4 VCC /2 GND GND F4 F15 F1 F4 F4 PGA PIN Q3 P5 Q4 N6 P6 Q5 P7 N7 Q6 P8 N8 N9 Q9 Q10 P9 P10 N10 Q11 P11 Q12 Q13 P12 N11 P13 Q14 N12 N13 P14 M13 N14 M14 L13 N15 L14 M15 K13 PIN NAME ENPHAC ENTIREG ENI MODPI/2PI CS CLK AD(1) AD(0) WR C(15) C(14) C(13) C(12) C(11) C(10) C(9) C(8) C(7) C(6) C(5) C(4) C(3) C(2) C(1) C(0) OUTMUX(1) OUTMUX(0) OER OEREXT OEIEXT OEI PACO DET0 DET1 RO(0) RO(1) BURN-IN SIGNAL F1 F4 F1 F16 F2 F0 F4 F3 F1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND V CC F11 F10 F0 F0 F0 F0 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 PGA PIN K14 L15 J14 J13 K15 H14 H13 G13 G15 F15 G14 F14 F13 E15 E14 D15 C15 D14 E13 C14 B15 D13 C13 B14 C12 B13 B12 C11 A13 B11 A12 C10 B10 A11 B9 C9 PIN NAME RO(2) RO(3) RO(4) RO(5) RO(6) RO(7) RO(8) RO(9) RO(10) RO(11) RO(12) RO(13) RO(14) RO(15) RO(16) RO(17) RO(18) RO(19) IO(0) IO(1) IO(2) IO(3) IO(4) IO(5) IO(6) IO(7) IO(8) IO(9) IO(10) IO(11) IO(12) IO(13) IO(14) IO(15) IO(16) IO(17) BURN-IN SIGNAL VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 VCC /2 PGA PIN A10 B8 C8 C7 A7 A6 B7 B6 C6 A5 B5 A4 A3 B4 C5 B3 A2 C4 C3 B2 A1 A9 A15 G1 J15 Q1 Q7 Q15 A8 A14 B1 H1 H15 P15 Q2 Q8 PIN NAME IO(18) IO(19) IMIN(18) IMIN(17) IMIN(16) IMIN(15) IMIN(14) IMIN(13) IMIN(12 IMIN(11) IMIN(10) IMIN(9) IMIN(8) IMIN(7) IMIN(6) IMIN(5) IMIN(4) IMIN(3) IMIN(2) IMIN(1) VC VCC VCC VCC VCC VCC VCC VCC GND GND GND GND GND GND GND GND BURN-IN SIGNAL VCC /2 VCC /2 F9 F8 F7 F6 F5 F4 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 None VCC None VCC VCC None VCC None GND None None GND GND None None GND
Die Characteristics
DIE DIMENSIONS: 350 mils x 353 mils x 19 1mils METALLIZATION: Type: Si-Al, or Si-Al-Cu Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE DENSITY: 1.6 x 105A/cm2
6

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